data sheet fc csp features: thermal performance: electrical: reliability: ? designed for high frequency applications ? 49 - 1800 ball counts ? target market - cell phones, hand-held electronics ? thin core laminate or ceramic package construction ? overmolded for handling and second level reliability ? accommodates package sizes from 3 mm to 15 mm ? flip chip bump pitches of 150 m min. for peripheral array, 250 m min. for area array ? available in 0.5 mm - 1.0 mm bga ball pitch, as well as lga interconnect ? minimum nominal package thickness of 0.80 mm for lga interconnect, 1.0 mm for 0.5 mm bga pitch, 1.2 mm for 0.8 mm pitch ? turnkey solution - design, bumping, bumped wafer probe, backgrind, assembly, test ? much better signal to noise ratio at higher frequencies (>1ghz) ? low inductance of flip chip bumps - short, direct signal path ? flexible customized substrate routing theta ja (cw) ? 8 x 8 mm, 64 lead package with 1.75 mm x 2.27 mm die, 0.8 mm pitch, 0.6 mm mold cap ? 0 lfpm, 4 layer pc board ? junction ambient thermal resistance = 48.1 c/w 8 x 8 mm body, 64 ld, 0.8 mm ball pitch min max inductance 0.26 nh 2.16 nh capacitance 0.18 pf 0.38 pf resistance 7 m ? 53.9 m ? simulated results @ at 100 mhz package level: ? laminate moisture jedec level 3 @ 240 c sensitivity 30 c/60% rh, 192 hours ? ceramic moisture jedec level 1 @ 260 c sensitivity 85 c/85% rh, 168 hours ? pct 121 c/100% rh, 96 hours ? temp/humidity 85 c/85% rh, 1000 hours ? high temp storage 150 c, 1000 hours ? temp cycle -55 c/+125 c, 1000 cycles board level: ? thermal cycle -40 c/+125 c, 1 cycle/hour, 3000 cycles* ? thermal cycle -40 c/+125 c, 2 cycles/hour, 2500 cycles* *data for 8 x 8 mm body, 64 lead, 0.33 mm pwb nsmd pad size fc csp packages: amkor technology is now offering the flip chip csp ( fc csp) package ? a flip chip solution in a csp package format. this package construction utilizes eutectic tin/lead (63sn/37pb) flip chip interconnect technology, in either area array or peripheral bump layout, replacing standard wirebond interconnect. the advantages of flip chip interconnect are twofold: it provides enhanced electrical performance over standard wirebond technology, and it allows for a smaller form factor due to increased routing density, the ability to use area array die bumps and the elimination of wirebond loops. current wafer bump technology and flip chip assembly process allows for a minimum of 150 m peripheral flip chip bumping, or 250 m area array bumping. the fc csp is based on amkor's proprietary chiparray ? bga (cabga) package construction, using cutting edge thin core laminate substrates. the package is assembled in strip format, gang molded and saw singulated for manufacturing efficiency and cost minimization. laser ablated solder mask technology, via-in-pad substrate structure, and thin core substrate panel processing allow for increased routing density and enhanced electrical performance, making the fc csp an attractive option for advanced csp applications where electrical performance is a critical factor. the fc csp is available in both thin core laminate substrate technology, as well as ceramic substrate technology. package size ranges from 3 mm to 15 mm, accommodating bga ball pitches from 0.5 mm to 1.0 mm. in addition to bga technology, the fc csp is also available in lga format, allowing for a lower minimum package thickness. the ceramic flip chip package provides maximum flexibility for designers for number of layers and routing. current production is from 300 - 1800 i/o in lga, bga or sci (solder column interposer) formats, 1.27 mm and 1.0 mm pitch. alsic lids can be attached for maximum thermal dissipation. laminate www.amkor.com visit amkor technology online for locations and to view the most current product information . ds577d rev date: 07?05
fc csp laminate process highlights die size (max) pkg size - 1 mm bump pitch (min) pkg size - 1 mm in-line 150 m minimum array 250 m standard materials package substrate hitachi fr5 e679 / bt bump 63/37 sn/pb encapsulant epoxy mold compound solder balls eutectic snpb test services ? program generation/conversion ? product engineering ? wafer sort ? -55 c to +165 c test available ? burn-in shipping jedec trays tape and reel services data sheet with respect to the information in this document, amkor makes no guarantee or warranty of its accuracy or that the use of such information will not infringe upon the intellectual rights of third parties. amkor shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it and no patent or other license is implied hereby. this document does not in any way extend or modify amkor?s warranty on any product beyond that set forth in its standard terms and conditions of sale. amkor reserves the right to make changes in its product and specifications at any time and withou t notice. www.amkor.com cross-section fc csp package offering (units in mm) body size pitch ball count matrix 8 x 8 1.0 49 full 9 x 9 1.0 64 full 10 x 10 1.0 81 full 11 x 11 1.0 100 full 12 x 12 1.0 121 full 13 x 13 1.0 144 full 14 x 14 1.0 169 full 15 x 15 1.0 196 full 6 x 6 0.8 49 full 7 x 7 0.8 64 full 8 x 8 0.8 64 full 8 x 8 0.8 81 full 9 x 9 0.8 100 full 10 x 10 0.8 144 full 11 x 11 0.8 169 full 12 x 12 0.8 196 full 3 x 3 0.5 25 full 4 x 4 0.5 36 full 5 x 5 0.5 48 2 row 5 x 5 0.5 64 full 6 x 6 0.5 64 2 row 6 x 6 0.5 84 3 row 7 x 7 0.5 80 2 row 7 x 7 0.5 108 3 row 8 x 8 0.5 96 2 row 8 x 8 0.5 132 3 row 9 x 9 0.5 156 3 row 10 x 10 0.5 180 3 row configuration options: fc bga (flip chip bga): moderate routing density, lowest cost flip chip package in intermediate ball counts. bare die or single piece lid. qualified with both bu and 4l thin core substrates. ball count range is 256 - 1900 and body size range is 17 - 45 mm. ceramic fc bga (ceramic flip chip bga): alumina or hitce flip chip packages with bga, lga, or sci interconnect format. capability for high layer count enables most flexible format for different ground and power planes. available in bare die, aisic lid, or low cost flat lid. qualified in body sizes ti 45 mm hitce (bga), 45 mm alumina (sci) and 31 mm alumina (bga). applications: the FCCSP package is targeted to high-performance workstations, servers, data communication products, internet routers and at high frequency and rf packaging applications where electrical performance is critical. the elimination of wirebond loops allows for a low inductance connection to the die, while the increased routing density enables optimized electrical paths for critical high frequency signal lines. the FCCSP is also an attractive option for portable and handheld electronics where, in addition to performance, package size is critical. ceramic fc bga
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